The present invention relates to a mask data generator applied for a graphics LSI (Large Scale Integrated circuit), and particularly to a mask data generator for generating mask data to be used for masking a sequence of drawing data to be written in a frame buffer with one access.
First, mask data generation performed in the graphics LSI is described.
FIG. 1 is a schematic diagram illustrating an example of the graphics LSI for drawing graphic images especially such as lines, rectangular frames or rectangular fills, having a command execution section 101, an address generator 102, a drawing data processor 103 and a mask data generator 104. The command execution section 101 generates control signals to be delivered to the address generator 102, the drawing data processor 103 and the mask data generator 104, according to parameters and command data transmitted from a CPU (Central Processor Unit) 100. The address generator 102 generates an access address indicating a start address of a frame buffer 105 from where a sequence of drawing data is written sequentially with one access. The drawing data processor 103 prepares the sequence of drawing data to be written in the frame buffer 105. The mask data generator 104 generates mask data according to the access address generated by the address generator 102 controlled by the command execution section 101. Each bit of the mask data corresponds to each byte of the sequence of drawing data and indicates if data of corresponding byte of the sequence of drawing data are to be replaced or not with data of corresponding address of the frame buffer 105.
For example, when logic of n-th lower bit of the mask data is `1`, data of n-th byte from the access address of the frame buffer 105 are replaced with data of n-th byte of the sequence of drawing data, while the data there are left as they are when the logic of the lower n-th bit of the mask data is `0`.
Therefore, it is important for the graphics LSI to generate the mask data with a sufficient speed.
There is a method for generating the mask data disclosed in a Japanese patent application laid open as a Provisional Publication No. 225453/'92, wherein the mask data generator 104 is provided with two registers for storing mask data to be used for masking a start data sequence and an end data sequence respectively.
Here, the start data sequence means a sequence of drawing data to be written with one access including data of a beginning part of each line data of a graphic image to be drawn, and the end data sequence means that including an ending part of the line data. When a rectangular fill is drawn, for example, every line data should be written at the same horizontal addresses. So, by preparing mask data for the start sequence and the end sequence separately, the mask data generation can be performed at a high speed making rise of the prepared mask data.
FIG. 6 is a block diagram illustrating configuration of the mask data generator according to the prior art for generating mask data of 128 bits, that is, mask data for masking a sequence of drawing data of 128 bytes to be written in the frame buffer 105 with one access.
Referring to FIG. 6, mask data of 128 bits for masking a start data sequence are supplied from a CPU 100 through bus lines 110 to be registered in a start mask register 202. In the same way, mask data of 128 bits for masking an end data sequence are registered in an end mask register 203.
Watching the access addresses generated by the address generator 102 of FIG. 1, a start mask control section 204 sends a signal to a start multiplexer 206 when access address of the start data sequence is found. The start multiplexer 206 selects and outputs the mask data stored in the start mask register 202 when it receives the signal from the start mask control section 204, while otherwise it outputs data of 128 bits, every logic thereof being `1`. In the same way an end multiplexer 207 selects and outputs the mask data stored in the end mask register 203 when an end mask control section 205 detects access address of the end data sequence generated by the address generator 102, and otherwise outputs mask data of 128 bits all having logic `1`.
An AND gate array 208 calculates logical products of the output of the start multiplexer 206 and that of the end multiplexer 207 to be output as the mask data of 128 bits for each sequence of drawing data.
However, according to the mask data generator of the prior art of FIG. 6, it takes four clock cycles for supplying data of 128 bits to be registered in the start mask register 202 as well as in the end mask register 203 through the bus lines 110 when width of the bus lines 110 is 32 bits parallel. This is a problem.
FIG. 7 is a block diagram illustrating another conventional example of the mask data generator 104 for generating mask data of 8 bits for masking a sequence of drawing data of 8 bytes, 64 bits, wherein mask data are generated from address data of a beginning pixel and address data of an ending pixel of line data.
In the example of FIG. 7, a first multiplexer 700 and a second multiplexer 701 are provided in place of the start mask register 202 and the end mask register 203 of FIG. 6, respectively.
The first multiplexer 700 selects and outputs one of eight bytes, `FF`, `FE`, `FC`, `F8`, `F0`, `E0`, `C0` and `80` in hexadecimal, according to logic of lower three bits 2:0! of address data of a beginning pixel to be drawn in a line memory of the frame buffer 105.
For example, when the lower three bits of the beginning pixel address indicate `001` in binary code, that is, when effective drawing data begins from second byte of the start data sequence of eight bytes, the first multiplexer 700 selects a byte of `FE`, in hexadecimal (hereafter expressed as `FEh`), that is, `1111 1110` in binary code (hereafter binary codes are expressed such as `1111 1110`), indicating that the first byte of the sequence of drawing data corresponding to the lowest bit `0` should be masked.
In the same way, the second multiplexer 701 selects and outputs one of eight bytes, `01h`, `03h`, `07h`, `0Fh`, `1Fh`, `3Fh`, `7Fh` and `FFh`, according to logic of lower three bits 2:0! of the ending pixel address.
Table 1 represents outputs of the first multiplexer 700 and the second multiplexer 701 relative to their control logic, that is, logic of lower three bits of the beginning pixel address or the ending pixel address.
Similarly with the mask data generator of FIG. 6, the start multiplexer 206 selects and output the byte data selected by the first multiplexer 700 when the start mask control section 204 detects an access address of the start data sequence generated by the address generator 102, and otherwise outputs byte data of `FFh`. The end multiplexer 207 selects and outputs the byte data selected by the second multiplexer 701 when the end mask control section 205 detects access address of the end data sequence, and otherwise outputs byte data of `FFh`. The mask data of eight bits to be output are obtained from the AND gate array 207 calculating logical products of the output of the start multiplexer 206 and that of the end multiplexer 208.
TABLE 1 ______________________________________ control output logic first multiplexer second multiplexer ______________________________________ 000b FFh = 1111 1111b 01h = 0000 0001b 001b FEh = 1111 1110b 03h = 0000 0011b 010b FCh = 1111 1100b 07h = 0000 0111b 011b F8h = 1111 1000b 0Fh = 0000 1111b 100b F0h = 1111 0000b 1Fh = 0001 1111b 101b E0h = 1110 0000b 3Fh = 0011 1111b 110b C0h = 1100 0000b 7Fh = 0111 1111b 111b 80h = 1000 0000b FFh = 1111 1111b ______________________________________
According to the method applied in the mask data generator of FIG. 7, there is no need to supply mask data through the bus lines, but a fairly large scale of circuit configuration becomes necessary if mask data of 128 bits, for example, are to be generated in the same way, since the first and the second multiplexers 700 and 701 should select data of 128 bits from 128 patterns of data of 128 bits, that is, 16,400 bits. This is another problem.